In recent years, the information processing amount required for digital electronic equipments is steadily increasing, and also the number of signal wirings in an equipment is increasing together with the increase of the information processing amount.
Therefore, much effort and time are required when a designer carries out a wiring process (wiring design) in a wiring region of a wiring design target such as an LSI, a printed board or the like by handwork, and a technique for automatically carrying out a wiring process (signal wiring) is required.
Thus, a technique is conventionally available wherein a wiring rule is produced based on information of parts connected in a net and automatic wiring is carried out in accordance with the wiring rule (refer to, for example, Japanese Patent Laid-Open No. 2000-227927; hereinafter referred to as Patent Document 1). An other technique is available wherein a design rule is determined using a sum total (evaluation cost) of critical are as determined from a plurality of layout data (refer to, for example, Japanese Patent Laid-Open No. 2004-172158; hereinafter referred to as Patent Document 2). A further technique is available wherein, where a constraint condition is not satisfied after disposition and wiring processes are automatically carried out, moderation information is added to the constraint condition and then it is decided again whether or not the constraint condition is satisfied (refer to, for example, Japanese Patent Laid-Open No. 2002-92059; hereinafter referred to as Patent Document 3).